machxo3d.

Enhance Secure Control Applications with Hardware Root-of-Trust and Dual Boot Capabilities

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通讯订阅

Builds on Proven MachXO3 Architecture– MachXO3D adds on immutable embedded security block, enhanced control functions, and expanded user flash memory up to 2700 kbits.

Highly Secured FPGA–Immutable security enables Hardware Root-of-Trust and pre-verified cryptographic functions such as ECDSA, ECIES, AES, SHA, HMAC, TRNG, Unique Secure ID and Public/Private Key Generation.

在设备双启动闪光灯上– No need for external memory for dual boot configuration. On device dual boot flash enables fail-safe programming and provides flexible in-field updates.

Features

  • Simplifies通过在平台上的第一个接通中集成信任根，最后的设备实现硬件安全性
  • Supports security throughout theproduct lifecycle包括设备制造和运输，平台制造，安装，操作和退役
  • 启用comprehensive通过提供数据安全，设备安全性，数据认证，设计安全和品牌保护来保护各种威胁
  • Programmable logic combined with secure dual boot configuration block provides灵活性during design implementation and enables secure updates after equipment deployment
  • 提供符合NIST SP 800-193的强大安全性和预先验证的加密功能PFRandCAVP.guidelines to protect non-volatile memory, detect malicious code and recover in case of corruption

跳到

安全

machxo3d.is NIST-CAVP certified and complies with NIST SP 800-193 PFR Guidelines

Lattice has completed the National Institute of Standards and Technology (NIST) Cryptographic Algorithm Validation Program (CAVP) certification for the MachXO3D™ cryptographic functions listed below. NIST CAVP provides validation testing of FIPS-approved and NIST-recommended cryptographic algorithms and their individual components. Federal Information Processing Standards (FIPS) is the U.S. federal government’s standard for cryptographic software.

MachXO3D建立硬件Root-of-Trust(ROT) to protect, detect and recover the device and other components from unauthorized firmware access throughout their systems’ lifecycle, from the point of manufacturing to end of life. These security functions are compliant with NIST SP 800-193 PFR guidelines and now certified with NIST-CAVP validation tests described in below table.

NIST-CAVP Certifications for MachXO3D™ cryptographic functions

Validation Number C998
Test Capabilities 描述
AES-ECB 方向：解密，加密
Key Length: 128, 256
ECDSA KEYGEN（186-4） 曲线：P-256
Secret Generation Mode: Testing Candidates
ECDSA SigGen (186-4) Capabilities:
曲线：P-256
Hash Algorithm: SHA2-256
Ecdsa Sigver（186-4） Capabilities:
曲线：P-256
Hash Algorithm: SHA2-256
HMAC DRBG 预测抵抗：没有
Capabilities:
模式：SHA2-256
Entropy Input: 256
Nonce: 256
个性化字符串长度：0
Additional Input: 0
Returned Bits: 256
HAC-SHA2-256 Mac：256
Key sizes < block size
KAS-ECC Function: Key Pair Generation
KAS-ECCCDH-Component Function: Key Pair Generation
SHA-256 Message Length: 8-65536 Increment 8

To see this certification on the NIST website,click here。

了解有关NIST COMP的更多信息，click here。

家庭表

machxo3d.Device Selection Guide
Features machxo3d.-4300 MachXO3D-9400.
LUTs 4300 9400
Distributed RAM (kbits) 3.4 73
EBR SRAM (kbits) 92. 432
UFM (kbits) 3.67/11223. 1088/26933.
PLLS. 2 2
Hardened Security Block 1 1
Oscillator 1 1
On-chip Dual-boot Yes Yes
I3C compatible I/O Yes1 Yes1
MIPI D-PHY Support2 Yes Yes
Core Vcc 2。5 - 3.3V 2。5 - 3.3V
Commercial Temperature Grade Yes Yes
Industrial Temperature Grade Yes Yes
High Performance / Low Power Option HC / ZC. HC / ZC.

1.银行3中的4对I / O，I3C动态拉动能力。
2。HC device only.
3.。When dual-boot is disabled, image space can be repurposed as extra UFM.

0.5 mm Spacing I/O Count
machxo3d.-4300 MachXO3D-9400.
72 QFN（10 mm x 10 mm） 58 (HC / ZC) 58 (HC / ZC)
0.8 mm Spacing I/O Count
machxo3d.-4300 MachXO3D-9400.
256-ball caBGA (14 mm x 14 mm) 206 (HC / ZC) 206 (HC / ZC)
400-ball caBGA (17 mm x 17 mm) 3.3.5 (HC / ZC)
484-ball caBGA (19 mm x 19 mm) 3.83 (HC)

示例解决方案

Secure Control PLD展开映像

Secure Control PLD

  • 使用安全控制PLD功能增强dual bootandhardware root-of-trusttosimplify实施全面，灵活和强大hardware security throughout product lifecycle.
Design Example: MachXO3D Secure Server展开映像

Secure Server

  • Hardened secure configuration block enables MachXO3D to protect, detect and recover itself from malicious attacks
  • FPGA fabric enables parallel processing capability to protect, detect and recover multiple platform firmware at the same time
  • Compliant with NIST SP 800 193 Platform Firmware Resiliency (PFR) guidelines
信任链条实施例子展开映像

信托链条

  • 硬件根源信任是保护整个系统的信任链中的第一个链接
  • 硬化器件配置引擎在上电时加密地验证MachXO3D的配置图像
  • 嵌入式安全块提供加密功能以在上电时验证其他平台固件
  • With instant-on capability MachXO3D is the first device to boot up securely on the platform and as such is an excellent anchor for Chain of Trust

设计资源

知识产权与参考设计

Simplify your design efforts by using pre-tested, reusable functions

应用笔记s

Learn how to get the most from our line-up of FPGAs / development boards

软件

完整的设计流，高易用性

开发套件和董事会

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

文档

快速参考
技术资源
Information Resources
Downloads
TITLE NUMBER 版 日期 格式 尺寸
Implementing High-Speed Interfaces with MachXO3D Usage Guide
 FPGA-TN-02065 0.90 6/16/2019 PDF 1.9 MB.
machxo3d.Hardware Checklist
 FPGA-TN-02104 0.9 5/21/2019 PDF 739.4 KB.
machxo3d.Programming and Configuration Usage Guide
 FPGA-TN-02069 0.9 5/21/2019 PDF 1.7 MB.
machxo3d.Soft Error Detection (SED)/Correction (SEC) Usage Guide
 FPGA-TN-02124 0.90 5/21/2019 PDF 1。1MB
Machxo3D Sysclock PLL使用指南
 FPGA-TN-02070 0.90 6/16/2019 PDF 1.8 MB.
machxo3d.sysI/O Usage Guide
 FPGA-TN-02068 0.90 6/16/2019 PDF 1。1MB
Memory Usage Guide for MachXO3D Devices
 FPGA-TN-02066 0.90 6/16/2019 PDF 4.5 MB
BGA包装的PCB布局建议
 FPGA-TN-02024 4.1 2019年5月5日 PDF 4.6 MB.
Power Decoupling and Bypass Filtering for Programmable Devices
 TN1068 1。0 5/1/2004 PDF 3.1。4 KB
在MachXO3D设备中使用硬化控制功能
 FPGA-TN-02117 1。1 8/28/2019 PDF 1.7 MB.
在MachXO3D设备中使用硬化控制功能Reference Guide
 FPGA-TN-02119 0.90 2011年8月5日 PDF 2.2 MB.
MachXO3D家庭数据表
 FPGA-DS-02026 1。0 12/10/2019 PDF 5 MB
machxo3d 256-pin cabga包迁移文件
 1。0 5/21/2019 CSV 15 KB
MachXO3D 72引脚QFN包迁移文件
 1。0 5/21/2019 CSV 4.7 KB.
machxo3d-4300引脚
 1。02 6/1/2020 CSV 17.5 KB.
Machxo3d-9400引脚
 1。0 5/21/2019 CSV 28.1 KB
TITLE NUMBER 版 日期 格式 尺寸
MachXO3D家庭数据表
 FPGA-DS-02026 1。0 12/10/2019 PDF 5 MB
TITLE NUMBER 版 日期 格式 尺寸
machxo3d.Embedded Security Block
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 5781 for detail instruction.		 FPGA-TN-02091 5/21/2019
Implementing High-Speed Interfaces with MachXO3D Usage Guide
 FPGA-TN-02065 0.90 6/16/2019 PDF 1.9 MB.
machxo3d.Hardware Checklist
 FPGA-TN-02104 0.9 5/21/2019 PDF 739.4 KB.
machxo3d.Programming and Configuration Usage Guide
 FPGA-TN-02069 0.9 5/21/2019 PDF 1.7 MB.
machxo3d.Soft Error Detection (SED)/Correction (SEC) Usage Guide
 FPGA-TN-02124 0.90 5/21/2019 PDF 1。1MB
Machxo3D Sysclock PLL使用指南
 FPGA-TN-02070 0.90 6/16/2019 PDF 1.8 MB.
machxo3d.sysI/O Usage Guide
 FPGA-TN-02068 0.90 6/16/2019 PDF 1。1MB
Memory Usage Guide for MachXO3D Devices
 FPGA-TN-02066 0.90 6/16/2019 PDF 4.5 MB
BGA包装的PCB布局建议
 FPGA-TN-02024 4.1 2019年5月5日 PDF 4.6 MB.
Power Decoupling and Bypass Filtering for Programmable Devices
 TN1068 1。0 5/1/2004 PDF 3.1。4 KB
在MachXO3D设备中使用硬化控制功能
 FPGA-TN-02117 1。1 8/28/2019 PDF 1.7 MB.
在MachXO3D设备中使用硬化控制功能Reference Guide
 FPGA-TN-02119 0.90 2011年8月5日 PDF 2.2 MB.
TITLE NUMBER 版 日期 格式 尺寸
machxo3d 256-pin cabga包迁移文件
 1。0 5/21/2019 CSV 15 KB
MachXO3D 72引脚QFN包迁移文件
 1。0 5/21/2019 CSV 4.7 KB.
machxo3d-4300引脚
 1。02 6/1/2020 CSV 17.5 KB.
Machxo3d-9400引脚
 1。0 5/21/2019 CSV 28.1 KB
TITLE NUMBER 版 日期 格式 尺寸
I2C to WISHBONE Configuration Interface Bridge - Documentation
 FPGA-RD-02190 1。0 5/16/2020 PDF 1。5 MB
i2c到汉语配置界面桥 - 源代码
 FPGA-RD-02190 1。0 5/16/2020 ZIP 1。3.MB
SPI to WISHBONE Configuration Interface Bridge - Documentation
 FPGA-RD-02191 1。0 5/16/2020 PDF 1.6 MB.
SPI to WISHBONE Configuration Interface Bridge - Source Code
 FPGA-RD-02191 1。0 5/16/2020 ZIP 1。3.MB
Using MachXO3D ESB to implement AES128/256 Encryption/Decryption
 FPGA-RD-02056 1。0 5/21/2019 PDF 781.8 KB
使用MachXO3D ESB实现AES128 / 256加密/解密 - 源代码
 1。0 5/21/2019 ZIP 712.9 KB.
Using MachXO3D ESB to implement ECC Key Pair Generation
 FPGA-RD-02057 1。0 1/10/2020 PDF 946 KB.
Using MachXO3D ESB to implement ECC Key Pair Generation - Source Code
 1。0 5/21/2019 ZIP 823.3 KB.
Using MachXO3D ESB to implement ECDSA Generation/Verification
 FPGA-RD-02053 1。0 5/21/2019 PDF 1 MB.
使用MachXO3D ESB实现ECDSA生成/验证 - 源代码
 1。0 5/21/2019 ZIP 974.6 KB
使用MachXO3D ESB实现ECIES加密/解密
 FPGA-RD-02055 1。0 5/21/2019 PDF 973.3 KB
使用MachXO3D ESB实现ECIES加密/解密 - 源代码
 1。0 5/21/2019 ZIP 911.8 KB
Using MachXO3D ESB to implement HMAC SHA256 - Documentation
 FPGA-RD-02052 1。0 5/21/2019 PDF 858.4 KB
使用MachXO3D ESB实现HMAC SHA256 - 源代码
 1。0 5/21/2019 ZIP 816.3 KB.
Using MachXO3D ESB to implement SHA256
 FPGA-RD-02054 1。0 5/21/2019 PDF 1000.5 KB
Using MachXO3D ESB to implement SHA256 - Source Code
 1。0 5/21/2019 ZIP 989.3 KB.
TITLE NUMBER 版 日期 格式 尺寸
格子MachXO3D orcad捕获原理图库（OLB）
 1。0 5/21/2019 ZIP 22。1KB
TITLE NUMBER 版 日期 格式 尺寸
machxo3d.Product Brief
 I0268 1。0 5/21/2019 PDF 567 KB
TITLE NUMBER 版 日期 格式 尺寸
BG256 XO3D
 1。0 5/21/2019 PDF 23.。2KB
BG400 XO3D
 1。0 5/21/2019 PDF 23.。3.KB
BG484 XO3D
 1。0 5/21/2019 PDF 23.。3.KB
TITLE NUMBER 版 日期 格式 尺寸
Building Comprehensive Hardware Security
 WP0018 1。0 5/21/2019 PDF 250.2 KB
TITLE NUMBER 版 日期 格式 尺寸
[BSDL] LCMXO3D-4300C CABGA256
 1。0 5/21/2019 BSM 47.3 KB.
[BSDL] LCMXO3D-4300C QFN72
 1。0 5/21/2019
[BSDL] LCMXO3D-9400C CABGA256
 1。0 5/21/2019 BSM 54.5 KB.
[BSDL] LCMXO3D-9400C CABGA400
 1。0 5/21/2019 BSM 65.8 KB
[BSDL] LCMXO3D-9400C CABGA484
 1。0 5/21/2019 BSM 70.8 KB
[BSDL] LCMXO3D-9400C QFN72
 1。0 5/21/2019 BSM 40.5 KB
TITLE NUMBER 版 日期 格式 尺寸
格子Machxo3d.
 1。0 5/21/2019 IBS 3.8.3 MB


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