Why is a DRC error generated associated with the PCI Core signal/pin serrn (SERR#)?
SERR# is defined as an Open-Drain pin in the PCI Local Bus Specifications. In certain PCI applications, a PCI agent might be required to monitor the SERR# pin so that the agent can properly respond to the system error condition.
When using one of the Lattice PCI IP cores targeting one of the Lattice FPGA families, it is possible the IO_TYPE for serrn (SERR#) has been set to PCI33, which does not allow OPENDRAIN as an option.
Since Open-Drain pin/signal is not subject to strict set-up/hold time requirements like the AD, C/BE# signals, the IO_TYPE for serrn can be changed to LVCMOS33 with the appropriate DRIVE.
For example, the constraint below can be included in the .lpf file.
IOBUF PORT "serrn" IO_TYPE=LVCMOS33 DRIVE=8 ;